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High Performance and Embedded Architecture and Compilation

High Performance and Embedded Architecture and Compilation is a science project.

Event research_grant eu_cordis:779656
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Key Facts

  • Start time: December 1, 2017[1]
  • End time: February 29, 2020[2]
  • Participant: Ghent University[3], eu_cordis_org:999655520[4], Chalmers University of Technology[5], eu_cordis_org:999995893[6], eu_cordis_org:999547074[7], University of Edinburgh[8], University of Pisa[9], RWTH Aachen University[10], Alternative Energies and Atomic Energy Commission[11], Arm Holdings[12], eu_cordis_org:999751938[13], eu_cordis_org:940177448[14], eu_cordis_org:999614489[15]
  • Short name: HiPEAC[16]
  • Budget: 2,600,000 euro[17]
  • Funding scheme: Horizon 2020[18]

References

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Direct Wikidata claims

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  17. [17] ↑ . wikidata.org.
  18. [18] ↑ . wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). High Performance and Embedded Architecture and Compilation. Retrieved October 8, 2026, from https://4ort.xyz/entity/high-performance-and-embedded-architecture-and-compilation-eu-cordis-779656
MLA “High Performance and Embedded Architecture and Compilation.” 4ort.xyz Knowledge Graph, 4ort.xyz, 8 Oct. 2026, https://4ort.xyz/entity/high-performance-and-embedded-architecture-and-compilation-eu-cordis-779656.
BibTeX @misc{4ortxyz_high-performance-and-embedded-architecture-and-compilation-eu-cordis-779656_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{High Performance and Embedded Architecture and Compilation}}, year = {2026}, url = {https://4ort.xyz/entity/high-performance-and-embedded-architecture-and-compilation-eu-cordis-779656}, note = {Accessed: 2026-10-08}}
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