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Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures
Research article (IEEE Transactions on Electron Devices, 2021) · cited 28× · AI/ML
Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures
Summary
Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures is a scholarly article[1].
Key Facts
Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures's instance of is recorded as scholarly article[2].
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APA4ort.xyz Knowledge Graph. (2026). Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures. Retrieved May 24, 2026, from https://4ort.xyz/entity/analog-figures-of-merit-of-vertically-stacked-silicon-nanosheets-nmosfets-with-two-different-metal-gates-for-the-sub-7-n
MLA“Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/analog-figures-of-merit-of-vertically-stacked-silicon-nanosheets-nmosfets-with-two-different-metal-gates-for-the-sub-7-n.
BibTeX@misc{4ortxyz_analog-figures-of-merit-of-vertically-stacked-silicon-nanosheets-nmosfets-with-two-different-metal-gates-for-the-sub-7-n_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures}}, year = {2026}, url = {https://4ort.xyz/entity/analog-figures-of-merit-of-vertically-stacked-silicon-nanosheets-nmosfets-with-two-different-metal-gates-for-the-sub-7-n}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): Analog Figures of Merit of Vertically Stacked Silicon Nanosheets nMOSFETs With Two Different Metal Gates for the Sub-7 nm Technology Node Operating at High Temperatures — https://4ort.xyz/entity/analog-figures-of-merit-of-vertically-stacked-silicon-nanosheets-nmosfets-with-two-different-metal-gates-for-the-sub-7-n (retrieved 2026-05-24)
