An inter-layer interconnect BIST solution for monolithic 3D ICs
Research article (2018 IEEE 36th VLSI Test Symposium (VTS), 2018) · cited 10× · AI/ML
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- [2] ↑ An inter-layer interconnect BIST solution for monolithic 3D ICs — instance of (P31): scholarly article. wikidata.org.
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@misc{4ortxyz_an-inter-layer-interconnect-bist-solution-for-monolithic-3d-ics_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{An inter-layer interconnect BIST solution for monolithic 3D ICs}}, year = {2026}, url = {https://4ort.xyz/entity/an-inter-layer-interconnect-bist-solution-for-monolithic-3d-ics}, note = {Accessed: 2026-05-24}}
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