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A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS

Research article (IEEE Transactions on Circuits & Systems II Express Briefs, 2019) · cited 16× · AI/ML
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A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS

Summary

A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS is a scholarly article[1].

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  • A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS's instance of is recorded as scholarly article[2].

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  1. [2] ↑ . wikidata.org.

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  1. [1] ↑ . Wikidata. wikidata.org.

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APA 4ort.xyz Knowledge Graph. (2026). A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-fully-integrated-25-gb-s-low-noise-tia-cdr-optical-receiver-designed-in-40-nm-cmos
MLA “A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-fully-integrated-25-gb-s-low-noise-tia-cdr-optical-receiver-designed-in-40-nm-cmos.
BibTeX @misc{4ortxyz_a-fully-integrated-25-gb-s-low-noise-tia-cdr-optical-receiver-designed-in-40-nm-cmos_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A Fully Integrated 25 Gb/s Low-Noise TIA+CDR Optical Receiver Designed in 40-nm-CMOS}}, year = {2026}, url = {https://4ort.xyz/entity/a-fully-integrated-25-gb-s-low-noise-tia-cdr-optical-receiver-designed-in-40-nm-cmos}, note = {Accessed: 2026-05-24}}
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