Home ›
Entities
› academia
› A 188fs<sub>rms</sub>-Jitter and −243d8-FoM<sub>jitter</sub> 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
A 188fs<sub>rms</sub>-Jitter and −243d8-FoM<sub>jitter</sub> 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
Research article (2022 IEEE International Solid- State Circuits Conference (ISSCC), 2022) · cited 23× · AI/ML
A 188fsrms-Jitter and −243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector
Summary
A 188fsrms-Jitter and −243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector is a scholarly article[1].
Key Facts
A 188fsrms-Jitter and −243d8-FoMjitter 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector's instance of is recorded as scholarly article[2].
References
Programmatic citations — every numbered marker resolves to a verifiable graph row below.
Use these citations when quoting this entity in research, articles, AI prompts, or wherever provenance matters. We aggregate Wikidata + Wikipedia + authoritative open-data sources; the stitched, scored, cross-referenced view is what 4ort.xyz contributes.
APA4ort.xyz Knowledge Graph. (2026). A 188fs<sub>rms</sub>-Jitter and −243d8-FoM<sub>jitter</sub> 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-188fs-sub-rms-sub-jitter-and-243d8-fom-sub-jitter-sub-5-2ghz-ring-dco-based-fractional-n-digital-pll-with-a-1-8-dtc-ra
MLA“A 188fs<sub>rms</sub>-Jitter and −243d8-FoM<sub>jitter</sub> 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-188fs-sub-rms-sub-jitter-and-243d8-fom-sub-jitter-sub-5-2ghz-ring-dco-based-fractional-n-digital-pll-with-a-1-8-dtc-ra.
BibTeX@misc{4ortxyz_a-188fs-sub-rms-sub-jitter-and-243d8-fom-sub-jitter-sub-5-2ghz-ring-dco-based-fractional-n-digital-pll-with-a-1-8-dtc-ra_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A 188fs<sub>rms</sub>-Jitter and −243d8-FoM<sub>jitter</sub> 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector}}, year = {2026}, url = {https://4ort.xyz/entity/a-188fs-sub-rms-sub-jitter-and-243d8-fom-sub-jitter-sub-5-2ghz-ring-dco-based-fractional-n-digital-pll-with-a-1-8-dtc-ra}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A 188fs<sub>rms</sub>-Jitter and −243d8-FoM<sub>jitter</sub> 5.2GHz-Ring-DCO-Based Fractional-N Digital PLL with a 1/8 DTC-Range-Reduction Technique Using a Quadruple-Timing-Margin Phase Selector — https://4ort.xyz/entity/a-188fs-sub-rms-sub-jitter-and-243d8-fom-sub-jitter-sub-5-2ghz-ring-dco-based-fractional-n-digital-pll-with-a-1-8-dtc-ra (retrieved 2026-05-24)
