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A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low V<inf>MIN</inf> applications
Research article (2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), 2016) · cited 13× · AI/ML
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low V<inf>MIN</inf> applications
Summary
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low V<inf>MIN</inf> applications is a scholarly article[1].
Key Facts
A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low V<inf>MIN</inf> applications's instance of is recorded as scholarly article[2].
References
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APA4ort.xyz Knowledge Graph. (2026). A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low V<inf>MIN</inf> applications. Retrieved May 24, 2026, from https://4ort.xyz/entity/a-16nm-dual-port-sram-with-partial-suppressed-word-line-dummy-read-recovery-and-negative-bit-line-circuitries-for-low-v-
MLA“A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low V<inf>MIN</inf> applications.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/a-16nm-dual-port-sram-with-partial-suppressed-word-line-dummy-read-recovery-and-negative-bit-line-circuitries-for-low-v-.
BibTeX@misc{4ortxyz_a-16nm-dual-port-sram-with-partial-suppressed-word-line-dummy-read-recovery-and-negative-bit-line-circuitries-for-low-v-_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low V<inf>MIN</inf> applications}}, year = {2026}, url = {https://4ort.xyz/entity/a-16nm-dual-port-sram-with-partial-suppressed-word-line-dummy-read-recovery-and-negative-bit-line-circuitries-for-low-v-}, note = {Accessed: 2026-05-24}}
LLM promptAccording to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): A 16nm dual-port SRAM with partial suppressed word-line, dummy read recovery and negative bit-line circuitries for low V<inf>MIN</inf> applications — https://4ort.xyz/entity/a-16nm-dual-port-sram-with-partial-suppressed-word-line-dummy-read-recovery-and-negative-bit-line-circuitries-for-low-v- (retrieved 2026-05-24)
