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16.2 A 76fs<inf>rms</inf> Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization

Research article (2019 IEEE International Solid- State Circuits Conference - (ISSCC), 2019) · cited 60× · AI/ML
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16.2 A 76fs<inf>rms</inf> Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization

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16.2 A 76fs<inf>rms</inf> Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization is a scholarly article[1].

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  • 16.2 A 76fs<inf>rms</inf> Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization's instance of is recorded as scholarly article[2].

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APA 4ort.xyz Knowledge Graph. (2026). 16.2 A 76fs&lt;inf&gt;rms&lt;/inf&gt; Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization. Retrieved May 24, 2026, from https://4ort.xyz/entity/16-2-a-76fs-lt-inf-gt-rms-lt-inf-gt-jitter-and-40dbc-integrated-phase-noise-28-to-31ghz-frequency-synthesizer-based-on-d
MLA “16.2 A 76fs&lt;inf&gt;rms&lt;/inf&gt; Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization.” 4ort.xyz Knowledge Graph, 4ort.xyz, 24 May. 2026, https://4ort.xyz/entity/16-2-a-76fs-lt-inf-gt-rms-lt-inf-gt-jitter-and-40dbc-integrated-phase-noise-28-to-31ghz-frequency-synthesizer-based-on-d.
BibTeX @misc{4ortxyz_16-2-a-76fs-lt-inf-gt-rms-lt-inf-gt-jitter-and-40dbc-integrated-phase-noise-28-to-31ghz-frequency-synthesizer-based-on-d_2026, author = {{4ort.xyz Knowledge Graph}}, title = {{16.2 A 76fs&lt;inf&gt;rms&lt;/inf&gt; Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization}}, year = {2026}, url = {https://4ort.xyz/entity/16-2-a-76fs-lt-inf-gt-rms-lt-inf-gt-jitter-and-40dbc-integrated-phase-noise-28-to-31ghz-frequency-synthesizer-based-on-d}, note = {Accessed: 2026-05-24}}
LLM prompt According to 4ort.xyz Knowledge Graph (aggregator of Wikidata, Wikipedia, and authoritative open-data sources): 16.2 A 76fs&lt;inf&gt;rms&lt;/inf&gt; Jitter and –40dBc Integrated-Phase-Noise 28-to-31GHz Frequency Synthesizer Based on Digital Sub-Sampling PLL Using Optimally Spaced Voltage Comparators and Background Loop-Gain Optimization — https://4ort.xyz/entity/16-2-a-76fs-lt-inf-gt-rms-lt-inf-gt-jitter-and-40dbc-integrated-phase-noise-28-to-31ghz-frequency-synthesizer-based-on-d (retrieved 2026-05-24)

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