10.7 A 6.75-to-8.25GHz 2.25mW 190fs<inf>rms</inf> integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS
Research article (2015 IEEE International Solid-State Circuits Conference - (ISSCC) Digest of Technical Papers, 2015) · cited 18× · AI/ML
Press Enter · cited answer in seconds
0 sources
10.7 A 6.75-to-8.25GHz 2.25mW 190fs<inf>rms</inf> integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS
Summary
10.7 A 6.75-to-8.25GHz 2.25mW 190fs<inf>rms</inf> integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS is a scholarly article[1].
Key Facts
- 10.7 A 6.75-to-8.25GHz 2.25mW 190fs<inf>rms</inf> integrated-jitter PVT-insensitive injection-locked clock multiplier using all-digital continuous frequency-tracking loop in 65nm CMOS's instance of is recorded as scholarly article[2].